CA Reading Notes:Appendix B

Memory stall cycles formula
CPU execution time formula
Address trace?
miss rates and miss penalties often different for reads and writes
Misses per instruction is architecture-dependent
Categories:
Fully associative—>Set associate—> Direct mapped

Vast majority: direct, two-way set, four-way set
blocks —> -way set

Addressing

Tags - check block in the set
Index - select the set
Block offset - data position in the block
The bits for tags and index are flexible according to the categories.

Replacement

3.5 categories

• Random

• LRU(Least recently used)

• FIFO(first in, first out)

• pseudo-LRU (Refer to B-9)

Writing

writes are often slower than reads.
reads could manipulate more bits than needed, but writes can’t.

• Write through—The information is written to both the block in the cache and to
  the block in the lower-level memory.
• Write back—The information is written only to the block in the cache. The
  modified cache block is written to main memory only when it is replaced.
  dirty bit (record whether modified in the cache)

As we will see, I/O and multiprocessors are fickle: they want write back for
processor caches to reduce the memory traffic and write through to keep the cache consistent with lower levels of the memory hierarchy.
avoid write stall , use write buffer

two options on a write miss:

• Write allocate—The block is allocated on a write miss, followed by the pre-
  ceding write hit actions. In this natural option, write misses act like read misses.
• No-write allocate—This apparently unusual alternative is write misses do not
  affect the cache. Instead, the block is modified only in the lower-level memory.

联系能力不够，再加上时间不集中，看的时候感觉还是理解的不是很清楚，挂两个中文知乎的链接。
这个说的比较泛化
这个集中于Cache，可以说是说的非常具体了，竟然是呢喃学长的CA读书笔记
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