Notes for Princeton ELE 475: Computer Arch
Reading List
- Chap1
- Appendix A
- H&P5 C-1 - C-26、C-30 - C-58、C-61 - C-81
- H&P5 B-1 - B-40
- H&P5 147 - 192, 197 - 202, 207 - 221,
- S&L 177 - 367,Tomasulo 算法
Review Part
register allocation
Pipeline
IF,DE,EX,MEM,WB
or F,D,X,M,W
Hazard
- Structural hazards: two instructions need the same hardware resource at the same time
- Schedule: explicitly avoids scheduling instructions
- Stall: stalls until earlier instruction is no longer using contended resource
- Duplicate: Add more hardware to design
Simple5-stage MIPS pipeline has no structural hazards specifically because ISA was designed that way
- Post title：Notes for Princeton ELE 475: Computer Arch
- Post author：Jackcui
- Create time：2024-03-09 16:54:48
- Post link：https://jackcuii.github.io/2024/03/09/CA/
- Copyright Notice：All articles in this blog are licensed under BY-NC-SA unless stating additionally.
Comments